Configuration

File Format

Configuration for vhdlfmt can be provided via command line flags, or YAML file.

The path to the YAML file is given by the --config option.

Example vhdlfmt.yml file:

printWidth: 120
tabWidth: 4
useTabs: false
uppercaseReserved: false
indentCase: true
vTabs: true

Options

This section contains all the available configuration options for vhdlfmt.

Print Width

Guide length for each output line.

This is not a hard limit; trailing comments are not considered, and in some circumstances lines will overflow this length without wrapping.

Default	CLI Flag	Config File
120	--print-width <int>	printWidth: <int>

Tab Width

Space characters per tab, when tab characters are not used.

Default	CLI Flag	Config File
4	--tab-width <int>	tabWidth: <int>

Use Tabs

Indent using tabs instead of spaces.

Alignment within lines is still achieved using spaces.

Default	CLI Flag	Config File
false	--use-tabs	useTabs: <bool>

Uppercase Reserved

Output VHDL reserved words in uppercase.

Default	CLI Flag	Config File
false	N/A	uppercaseReserved: <bool>

Example output:

-- uppercaseReserved: false
entity comp is
end entity comp;

-- uppercaseReserved: true
ENTITY comp IS
END ENTITY comp;

Indent Case

Indent inner clauses of a case statement.

Default	CLI Flag	Config File
true	N/A	indentCase: <bool>

Example output:

-- indentCase: true
case SM is
    when IDLE =>
        busy <= '0';
    when others =>
        busy <= '1';
end case;

-- indentCase: false
case SM is
when IDLE =>
    busy     <= '0';
when others =>
    busy     <= '1';
end case;

VTabs

Enable vertical alignment of related symbols, e.g. declarations, trailing comments, etc.

Default	CLI Flag	Config File
true	N/A	vTabs: <bool>

Example output:

-- vTabs: true
entity comp is
    generic (
        data_in_width :     natural := 8; -- Data width
        fifo_depth    :     natural := 32
    );
    port (
        clk           : in  std_logic;
        reset         : in  std_logic;    -- Active high
        data          : in  std_logic_vector(data_in_width - 1 downto 0);
        full          : out std_logic
    )
end entity comp;

-- vTabs: false
entity comp is
    generic (
        data_in_width : natural := 8; -- Data width
        fifo_depth : natural := 32
    );
    port (
        clk : in std_logic;
        reset : in std_logic; -- Active high
        data : in std_logic_vector(width - 1 downto 0);
        full : out std_logic
    )
end entity comp;